Business Wire

eTopus Technology Announces Innovative SerDes Technology for Data Center, Cloud, Edge, and 5G Base Stations

The eTopus scalable, adaptive, low-power architecture for high-speed interconnects is in production and supported by technology leader SiFive SAN JOSE, Calif.--(BUSINESS WIRE)--eTopus Technology, a ...
EDN

112-Gbps LR SerDes PHY Taps CTLE and Time Interleaved Flash ADC to Reduce ADC Resolution

The right balance of CTLE circuitry and flash ADC sizes and number play a key role in minimizing ADC bits to achieve minimum area and power. The design of a state-of-the-art 112-gigabits-per-second ...
Electronic Design

White Papers: Custom ADC at CERN | 6 SERDES Design & Verification Challenges | More

Electronic Design is dedicated to keeping design engineers informed of the latest advancements in the engineering community. As such, we thought you would have interest in these resources from Mentor ...
EDN

Collaboration validates 12G interconnect for high-speed IP

eTopus taps Amphenol ICC’s ExaMAX2 112-Gbps interconnect for its ADC/DSP-based serializer/deserializer (SerDes) IP. The combined products can be used for high-speed communications, machine learning, ...
Semiconductor Engineering

The Challenges Of Designing 28G And 56G SerDes IP

The industry move to 56 Gbps PAM4 is undoubtedly one of the greatest challenges currently facing SerDes IP designers and their customers. To begin with, shifting to 56 Gbps PAM4 immediately causes a ...