SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...

The Cadence custom/analog and digital implementation and signoff tools have been validated by TSMC on high-performance reference designs in order to provide customers with the fastest path to design ...

Companies to enable easy node-to-node migration for analog blocks with enhanced PDK across multiple FinFET processes to accelerate design closure Early customers seeing more than 2.5X design cycle ...

Cadence Design Systems CDNS announced that its digital and custom/analog flows had received certification on Intel's 16 FinFET process technology. Additionally, Cadence's design intellectual property ...

“As the developer of the industry’s first modular 14nm FinFET technology and one of the leaders at 20nm, we understand that enabling designs at these advanced process nodes requires innovative ...

Cadence Design Systems announced on December 1 that HiSilicon Technologies has signed an agreement to significantly expand its use of the Cadence digital and custom/analog flows for 16nm FinFET ...

Currently under development for the 16 FF+ process, the Cadence IP portfolio includes multiple high-speed protocols for several key memory, storage and interconnect standards critical in the ...

The next frontier in the electronics industry is the FinFET, a new type of multi-gate 3D transistor that offers tremendous power and performance advantages compared to traditional, planar transistors.

Semiconductor Engineering sat down to discuss how long FinFETs will last and where we will we go next with Vassilios Gerousis, Distinguished Engineer at Cadence; Juan Rey, Sr. Director of Engineering ...