0 comments on “ 90-nm FPGAs embed SerDes, physical coding sublayer block ” Leave a Reply You must Sign in or Register to post a comment.

Two core products, the 10 Gigabit Physical Coding Sublayer (PCS) and the Media Access Controller (MAC), are intended for use in Xilinx’s Virtex-II and Virtex-II Pro field programmable ...

For optical networks, the IEEE P802.3ba standard defines three sublayers: PCS (Physical Coding Sublayer), PMA (Physical Medium attachment) and PMD (Physical Medium Dependent). Both 40-Gbps and ...

100G Ethernet PCS IP The Synopsys 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a complete set of features that enable users to define an optimized ...

The fully integrated Physical Coding Sublayer (PCS), KR4 FEC and Media Access Controller (MAC) core for 25Gbps Ethernet applications are compliant with IEEE 802.3by standard.

The new multi-channel, multi-rate solutions include 1.6T MAC (Media Access Control) and PCS (Physical Coding Sublayer) Ethernet controllers, alongside 224G Ethernet PHY (physical layer) IP and ...

According to the group, the 800 GbE specification introduces a new media access control (MAC) and Physical Coding Sublayer (PCS). “It essentially re-purposes two sets of the existing 400GbE ...

The transceivers consist of the company’s PMA, the analog high-speed SerDes part, hard-coded logic from Microsemi (the physical coding sublayer, or “link layer”) and controllers that can be ...

The 800 GbE specification introduces a new media access control (MAC) and Physical Coding Sublayer (PCS).

The acquisition adds MAC (Medium Access Controller) and PCS (Physical Coding Sublayer) for 200G/400G and 800G Ethernet to Synopsys’ portfolio. The company also provides Time-Sensitive Networking, ...

The subsystem expands on Open-Silicon’s existing high speed chip-to-chip Interlaken interface IP to include Ethernet Physical Coding Sublayer (PCS), Flex Ethernet (FlexE) and multi-channel multi-rate ...