EDN

Interoperable DRC/LVS language standard accelerates physical verification turnaround time for advanced nodes

As Moore’s Law drives semiconductor manufacturers to deliver a consistent doubling of transistor counts every two years, the number of rules in the DRM (design rule manual) for advanced processes has ...
Electronic Design

In Verification, Physics Intrudes Forcefully At 28 nm

Getting physical The number of physical design rules has increased significantly since the 65-nm node. At 40 nm, foundry runsets totaled fewer than 1000 rules to be checked. At 28 nm, the number of ...
Semiconductor Engineering

Physical Verification In The Cloud

Cloud computing is no longer “the next big thing”; it has become a mainstream tool for business across many industries. Our own industry of IC Design and EDA, however, has been watching the cloud ...
Business Wire

Mentor Graphics Provides Design, Verification, Thermal and Test Solutions for TSMC’s CoWoS™ Reference Flow

WILSONVILLE, Ore.--(BUSINESS WIRE)--Mentor Graphics Corp. (NASDAQ: MENT) today announced IC physical design, verification, thermal analysis and test design tools that have been selected for TSMC’s new ...
Semiconductor Engineering

The Route To Faster Physical Verification And Better Designs

As we’ve moved to today’s leading-edge nodes, physical layout designers have faced more and more challenges to get their design to tape-out on schedule. Timing becomes increasingly difficult to ...
Design-Reuse

Automating Design Rule Waivers in SoC IP Reuse

(Intellectual property (IP) reuse, especially at the physical IP level, is a key component of the growing system-on-chip (SoC) ecosystem. However, with the increase in the amount and scope of custom ...
Design-Reuse

UMC Certifies Synopsys IC Validator Physical Verification Tool for 28 nm

MOUNTAIN VIEW, Calif. and HSINCHU, Taiwan, April 23, 2014 – Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic ...
EDN

Hierarchical physical design—issues and methodologies

In IC physical design, there is a tendency to focus on the synthesis and layout tasks, and to not give much consideration to the chip finishing tasks, at least not until the more pressing matters of ...
AOL

Mentor Graphics Provides Design, Verification, Thermal and Test Solutions for TSMC's CoWoS™ Referenc

WILSONVILLE, Ore.--(BUSINESS WIRE)-- Mentor Graphics Corp. (NAS: MENT) today announced IC physical design, verification, thermal analysis and test design tools that have been selected for TSMC's new ...